Neethu K Thilak is an experienced ASIC RTL Design Engineer at Netrasemi, where they refine RTL implementations and align with ASIC design flows. Since 2025, Neethu has also been serving as a Senior RTL Design Engineer at Infineon Technologies. They previously held positions as an ASIC Design Engineer and Intern at Netrasemi, and as a Graduate Engineering Trainee at Bharat Sanchar Nigam Limited. Neethu earned a Master’s degree in Electronics Design Technology from the National Institute of Electronics & Information Technology and a Bachelor of Technology in Electronics and Communications Engineering from Vidya Academy of Science & Technology.
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