Ayushi Tripathi

Ayushi Tripathi is an experienced RTL Design Engineer currently at Renesas Electronics since October 2025, following a role as Senior R&D Engineer at Logic Fruit Technologies from July 2022 to October 2025, where responsibilities included work on PCIE/CXL (Gen6/CXL3) testing equipment and protocol analysis. Ayushi holds a B.Tech in Electrical Engineering from Bundelkhand Institute of Engineering and Technology, obtained in 2022, and a Diploma in Electrical Engineering from Government Polytechnic Kanpur, completed in 2018.