Shree Tharaney

Shree Tharaney is a verification engineer with 3 years of experience in Intellectual Property (IP) verification. Currently, Shree works as a Senior Design Engineer in verification on a CXL project at Tessolve, having previously held a position at Marvell Technology. Shree's expertise includes SystemVerilog, UVM, and APB and AXI bus protocols, and Shree has contributed to defining design and verification methodologies. Shree holds a Bachelor's degree in Electrical, Electronics and Communications Engineering from Kumaraguru College of Technology and a Diploma in the same field from PSG College of Technology.