Abey Chandran

Abey Chandran is a Hardware Engineer with extensive expertise in Design Verification within the VLSI technology sector. With experience in SV, UVM, UPF, and low-power verification methodologies, they have worked as a CPU Verification Engineer at MediaTek and a Design Verification Engineer at both Excelmax Technologies and LX Semicon. Abey also served as a Jr Research Fellow at TrEST Research Park, focusing on RISC-V based SOC verification for electric vehicles. Currently, Abey is a Silicon Engineering Specialist at Accenture, where they continue to apply their skills in the field. They hold a Bachelor of Technology in Telecommunications Engineering from Cochin University of Science and Technology.