ANUSHA B

Anusha B is a Verification Engineer with a strong foundation in VLSI design and verification. They began their career as an ASIC Design and Verification intern at Maven Silicon in 2017 and subsequently held positions as a Verification Engineer at Cientra and Wipro. Currently, Anusha is a Senior Design Engineer II at ACL Digital. They possess knowledge of various protocols including AHB, APB, UART, and SPI, along with expertise in cache technologies. Anusha earned a Bachelor of Technology in Electronics and Communications Engineering from G.Pulla Reddy Engineering College and a certification in VLSI Design & Verification from Maven Silicon Softech Pvt Ltd.