Moneesh Kumar Devangam

Moneesh Kumar Devangam is a verification lead and senior architect at ACL Digital, with a strong background in the semiconductors industry. Previously, Moneesh served as a verification manager at SASIC Technologies Private Limited from 2018 to 2023, and held positions as a design engineer at Masamb Electronics Systems and a senior verification engineer at Altran/SiCon Design Technologies Pvt. Ltd. Moneesh's technical expertise includes timing closure, automatic test pattern generation (ATPG), and FPGA design, supported by a B.Tech in Electronics and Communication Engineering and a P.G. Diploma in FPGA Designing from Sandeepani School for VLSI Design.