Sidharth Mehta is a Design Engineer in the RTL design domain with over 9 years of experience, specializing in CDC, RDC, and Lint. They began their career as a Research Intern at CSIR-CEERI, later working as a Design Engineer at Bit Mapper Integration Technologies and NXP Semiconductors. Sidharth contributed to FPGA-based applications for the Ministry of Defence of India and served as a Technical Lead at UST, focusing on digital design and IP maintenance activities. Currently, Sidharth holds the position of Senior Technical Lead at ACL Digital, continuing to advance their expertise in the field.
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