Moshe Refaeli

Moshe Refaeli is a seasoned professional in semiconductor design and development, currently serving as the principal R&D FPGA at ADVA Optical Networking since 2010, focusing on FPGA development for international communication projects. Previously, Refaeli held senior ASIC designer roles at Valens Semiconductor and Siverge Networks from 2007 to 2010 and 2005 to 2007, respectively, contributing to significant advancements in mixed-signal ASICs and traffic management solutions. Earlier experience includes leading ASIC teams at Adimos and VLSI teams at Virata, alongside a leadership role at Motorola Semiconductor where Refaeli managed VLSI device development for cellular handsets. Moshe Refaeli earned a B.Sc. in Electronics from Tel Aviv University between 1989 and 1993.