Amit Apte

Amit Apte is a Fellow Silicon Design Engineer at Advanced Micro Devices, currently focused on RTL design for the Distributed Memory Controller, System Level Cache Coherence, and the Directory Cache in AMD processors. With over six years of design verification experience, Amit has contributed significantly to advanced microprocessor designs, specializing in functional verification and RTL design. Amit's educational background includes a Bachelor of Engineering in Electronics from the University of Mumbai and a Master of Science in Electrical Engineering with a focus on Computer Engineering from the University of Maryland.