Amit Mehra

Amit Mehra is a Fellow at AMD with several years of experience in the computer chip industry, including significant expertise in clock architecture, RTL design, program management, post-silicon debug, top-level chip composition, and circuit design. Previously, Amit held roles at Hewlett-Packard as a Hardware Design Engineer and System Program Manager, and at Intel as a Program Manager and Clock Architect/RTL Designer. Amit earned a Bachelor of Science degree in Electrical and Electronics Engineering from Caltech and a Master of Engineering degree from Stanford University.