Cacy Yi

Cacy Yi is currently an MTS IC Design Engineer at AMD, where they focus on synthesis, timing optimization, and static timing analysis. They previously worked as a Physical Design Engineer at Avago Technologies from 2012 to 2014, where they handled various aspects of physical design, including floor planning and timing closure. Prior to that, Cacy was an IC Design Engineer at JingJia Microelectronics Pte Ltd from 2009 to 2012, contributing to floor planning and physical verification processes. Cacy also spent time at GLOBALFOUNDRIES as a Design Enablement Engineer from 2015 to 2018, developing tech files for process design kits. Their expertise includes RTL and schematic circuit design, as well as analog IC layout.