Chad Larson is a Post-Silicon Validation Engineer at AMD, where they lead validation for CXL IP in EPYC server chips. With a focus on the I/O subsystem of IBM Power servers, they have contributed to five generations of Power machines, addressing I/O-related issues from initial validation through product launch. Previously, Chad held roles at Dell EMC, enhancing the NVMe subsystem on PowerEdge servers and validating RAID controllers. They earned a Master of Science from the University of Texas at Austin and a Bachelor of Science from Iowa State University.
Location
Austin, United States
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