Daniel Lau is an accomplished CPU Performance Engineer at AMD since April 2023, previously serving as a Field Application Engineer. Prior to joining AMD, Daniel Lau worked at Xilinx from May 2012 to March 2023, focusing as a Field Applications Engineer in Communications and Data Center and as a Strategic Applications Engineer. Daniel Lau's career also includes experience at Fortinet from February 2007 to May 2012 as a Senior ASIC Design Engineer and Intermediate ASIC Design Engineer, where responsibilities included research and design related to networking protocols and ASIC implementations. Earlier experience at Pixelworks as an IC Design Engineer involved the verification of the Pearl chip and development of various IP blocks. Daniel Lau holds a Bachelor of Science in Electrical Engineering from the University of California, Berkeley, a Master of Science in Electrical Engineering from San José State University, and has completed studies at De Anza College and SFXC.
This person is not in the org chart
This person is not in any teams
This person is not in any offices