Deepesh John

Deepesh John is currently a Fellow Design Engineer at AMD, specializing in clocking architecture, SRAM design, and electrical analysis, including electromigration and low power design. Previously, Deepesh served as a Member of Technical Staff at AMD from 2006 to 2020, where they led clocking efforts for next-generation cores and caches, and managed 8T SRAM macro development. Deepesh gained early experience as an intern in R&D at ARM in 2005. They hold a BE in Electrical & Electronics from the Birla Institute of Technology and Science, Pilani and an MS in Electrical Engineering from the University of Michigan.