Eric Dixon

Eric Dixon is a Senior Member of Technical Staff at AMD, specializing in RTL design for next-generation CPU Floating Point architecture. They previously served as a Senior Design Engineer in Physical Design at AMD, where they contributed to L3 Cache design and led initiatives in instruction decode and micro-op cache for next-generation CPU designs. Their earlier experience includes engineering roles at Intel and Harris RF Communications, along with systems engineering at Viewpoint Systems. Eric holds a BS/MS in Electrical Engineering from the Rochester Institute of Technology.