Eric Stubblefield

Eric Stubblefield is a Senior ASIC Design Verification Engineer with extensive experience in constrained random verification for integrated circuit designs. They have held significant roles at leading technology companies including AMD, Seagate Technology, and Hewlett Packard, where they have led functional verification and post-silicon validation teams, developed UVM and VMM environments, and created comprehensive verification plans and schedules. Currently, Eric serves as a Principal Member of Technical Staff at AMD. They hold both a Bachelor's and a Master's degree in Electrical Engineering from the University of Tennessee, Knoxville, and Georgia Institute of Technology, respectively.