Jasmeet Singh is a dedicated Physical Design Engineer with over 10 years of experience and a Master's in VLSI design. Currently a PMTS Silicon Design Engineer at AMD since 2024, Jasmeet previously contributed to several APU and GPU tape-outs while at AMD and Xilinx. Jasmeet has a strong background in custom place and route scripting, bus planning, and architectural physical planning, complemented by a history of involvement in industry conferences. They have presented work at notable events, focusing on complex clocking structures and hierarchical design challenges.
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