Jay Kapasi

Jay Kapasi has extensive experience in engineering and technology, beginning with a role as a Software Engineer Intern at Tata Consultancy Services. Subsequent positions include Teaching Assistant at Dhirubhai Ambani Institute of Information and Communication Technology, Design Engineer at Bit Mapper Integration Technologies Pvt. Ltd, Module Lead at Mistral Solutions Pvt. Ltd, Senior Design Engineer at Xilinx, and Senior Validation Engineer at Microsemi Corporation, before becoming a MTS Silicon Design Engineer at AMD. Notable skills include FPGA RTL Design, Embedded C coding, and high-speed FPGA SERDES validation. Jay Kapasi holds a Master of Technology in VLSI and Embedded Systems and a Bachelor of Engineering in Information Technology, both accompanied by high academic achievements.