Jiang Luo is currently the Manager of ASIC/Layout Engineering at AMD, where they focus on front-end verification methodology, architectures, flows, and tools for modern large designs. Prior to this role, Jiang served as a Digital IC Lead at sili_startup and as a Senior Design Verification Engineer at AMD, where they developed graphics and system module test plans. Jiang holds a Master's degree in Electronics with a specialization in IC Design from Zhejiang University, completed in 2007.
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