Lakshay .

Lakshay is a Silicon Design Engineer 2 at AMD, where they focus on AT modeling of NoC IPs since 2022. Previously, they served as a Software Engineer at Cadence Design Systems, working on LT TLM models of PCIe CXL and UCIe from 2021 to 2022. Lakshay also gained experience as an intern at CDAC in 2020, contributing to a project for the Bengaluru Metro Rail Corporation. They hold a Bachelor of Technology in Electronics and Communications Engineering from the National Institute of Technology Kurukshetra, which they completed in 2021.