Mark Kelley

Mark Kelley is a Principal Engineer at AMD, where they lead RTL methodology for custom and synthesized designs and develop a power-aware flow for Verilog models. Previously, Mark held positions as a Senior Hardware Design Engineer at EFI and a Principal Engineer at Xilinx, contributing to multimillion gate designs and complex digital signal processing filters. They also worked as a Senior Hardware Engineer at Coherent Medical and KLA-Tencor, focusing on FPGA design and timing engines. Mark is currently pursuing a degree at California Polytechnic State University-San Luis Obispo.