Nirav Jain is a Formal Verification Engineer at Cerium Systems since August 2021, specializing in formal test plan creation, formal property verification, and coverage using SystemVerilog assertions and JasperGold software. Previously, Nirav Jain served as a Research Intern at IIT Patna from January to June 2021, focusing on the FPGA implementation of the CAN protocol and its security aspects related to Physical Unclonable Functions. Nirav Jain earned a Bachelor of Engineering degree in Electronics Engineering from Shri Ramdeobaba College of Engineering and Management in 2021.
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