Patrick Wu

Patrick Wu is a dedicated and organized Sr. Design Engineer at AMD, with 10 years of experience in ASIC/hardware testing and post-silicon validation. They developed and executed validation test plans for AMD's PCIe IP block and coordinated efforts across various teams to address issues during silicon bring-up. Previously, Patrick served as a Field Application Engineer at King Tiger Technology, where they developed test plans for DDR3 memory production and provided engineering support to customers. They also gained valuable experience as a Teaching Assistant at the University of Toronto and completed an internship at ATI Technologies. Patrick is currently pursuing both a Bachelor’s and Master’s degree in Electrical Engineering and Electronics from the University of Toronto.