Pavan Kumar

Pavan Kumar is a seasoned engineering professional with extensive experience in semiconductor design and architecture. Currently serving as a Principal Member of Technical Staff at AMD since December 2023, Pavan specializes in NoC/Infinity Fabric design. Prior to this role, Pavan held positions at Achronix Semiconductor Corporation as a Senior Member of Technical Staff and Senior Engineer, focusing on Network on Chip micro-architecture and RTL design. Previous experience includes a Principal Engineer role at Rambus, where Pavan contributed to the logic design of DDR5 RCD buffer chips, and a Senior Design Engineer position at Samsung Electronics, responsible for logic design of HBM DRAM Buffer die and advancements in Processing in Memory concepts. Pavan began a career at Intel as a Component Design Engineer, specializing in SOC design. Pavan holds a Master's degree in Electrical Engineering from the Indian Institute of Technology, Bombay, and a Bachelor of Technology in Electrical and Electronics Engineering from Jawaharlal Nehru Technological University.