思阳 王 is a Senior FPGA Engineer with expertise in FPGA+AI, FPGA cloud services, and heterogeneous computing. They currently work at AMD as an MTS Software Development Engineer since 2024. Previously, 思阳 was an FPGA Algorithm Engineer at 银河水滴科技(北京)有限公司 from 2017 to 2018, and then served as a Senior Software Engineer focused on Vitis Libraries at 賽靈思 from 2018 to 2025. They hold two master's degrees in Information, Production and System and Telecommunications Engineering, as well as a bachelor's degree in Telecommunications Engineering from 电子科技大学.
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