田渊

渊田 is a Technical Leader at 思科, with over 13 years of experience in ASIC/FPGA design, particularly in Ethernet communication chips and internal IO hubs. They have held a SMTS position at AMD since 2015 and contribute as PMTS at Quantenna Communications. Previously, they served as a Manager at Cortina Systems from 2008 to 2015, where they built and managed design and verification teams in Shanghai, focusing on traffic management modules. 渊田 earned a master's degree in Microelectronics from 东南大学 between 2000 and 2002.