王宏燕

宏燕 王 is a Sr. Layout Design Engineer at AMD, where they focus on DFT verification and ATPG processes. They have previously worked as a Logic Design and Verification Engineer at GigaDevice Inc. from 2012 to 2016, where they handled RTL and timing verification and contributed to design discussions. 宏燕 王 holds a Master’s degree in Microelectronics from NUDT and a Bachelor’s degree in Electronic Information Science and Technology from Jilin University.