Prabal D.

Prabal D. is a highly skilled engineer with extensive experience in design verification and embedded network software development. At AMD, Prabal served as a Member of Technical Staff, focusing on verifying next-generation FPGA architectures and developing robust testbench systems. Prior to this, Prabal held roles as a Senior Design Verification Engineer and Design Verification Engineer, where responsibilities included validating high-speed pathways and writing test cases for I/O specifications. Experience at North Carolina State University included positions as an FPGA Engineer and Graduate Teaching Assistant, where coursework on parallel computer architecture was complemented by the development of cache coherence protocols. An internship at MaxLinear involved creating Verification IP for PCS Autonegotiation in a UVM environment. Earlier career work at AppliedMicro focused on embedded network software for data center devices. Prabal holds a Master's degree in Computer Engineering from North Carolina State University.