Samuel A.

Samuel A. is a Senior Synthesis & STA Engineer at AMD, since July 2023, specializing in PrimeTime Static Timing Analysis, stringent waiver development, formal equivalence checking, and timing constraints development. Prior to this, Samuel worked as a Physical Design Engineer at Intel Corporation from July 2022 to June 2023, where responsibilities included executing place and route methodologies, floorplanning, and optimizing chip area for performance and power targets. Earlier experience includes serving as a Hardware Engineer Intern at Intel Corporation in 2021, focusing on formal equivalency checking and LINT checks, and as an Engineering Peer Mentor at University College Dublin from September 2019 to May 2020. Samuel holds a Master of Engineering in Electronic and Computer Engineering and a Bachelor of Science in Electrical and Electronics Engineering, both from University College Dublin.