Sushmitha Ramesh

Sushmitha Ramesh is a Senior Physical Design Engineer at AMD since April 2017, specializing in block and fullchip Static Timing Analysis (STA) constraint development and verification. Prior to this role, Sushmitha worked at Micron Technology as a Physical Design Engineer and Yield and Integration Engineer, focusing on Six Sigma methodologies for process improvement and data analysis. Experience includes a tenure at GLOBALFOUNDRIES as a Yield & Integration Engineer, where Sushmitha engaged in advanced CMOS technology projects and yield enhancement activities. Earlier positions include software testing at Tata Consultancy Services and project engineering at Entech, showcasing a diverse skill set across electrical engineering and project management. Sushmitha holds a Master of Science in Electrical Engineering with a focus on Microelectronics from the National University of Singapore and a Bachelor of Engineering in Electrical and Electronics from Anna University Chennai.