Teck Chee Loo

Teck Chee Loo is the Senior Manager of Silicon Design Engineering at AMD, a position held since 2022. Previously, Teck Chee managed the Singapore IC Layout Team at Xilinx from 2008 to 2022, where they led high-speed SerDes layout development projects and drove layout methodology improvements. Teck Chee also worked as an engineer at Intel and Altera between 2004 and 2007, focusing on FPGA layout. They earned a degree in Electrical Engineering from Universiti Tenaga Nasional in 2004.