Victor Wu

Victor Wu is a Principal Member of Technical Staff at AMD, where they co-lead the development of the SmartNIC compute offload accelerator engine since 2020. Prior to this role, Victor held several positions at Xilinx, including Senior Staff Design Engineer, where they co-led the development of the Xilinx Deep Learning Engine and served as the technical lead for the ML Engine IP on Versal AI. Earlier in their career, they worked as a Senior Logic Design Engineer and Logic Design Engineer at Intel Corporation, focusing on power management and memory unit design for Xeon Server Processors. Victor earned a B.S. in Electrical Engineering and Computer Sciences from the University of California, Berkeley, and pursued further studies in Computer Engineering at Stanford University.