William Siddeley

William Siddeley is a Senior Silicon Design Engineer at AMD, where they focus on full-stack development of a regression management platform and design verification of AMD’s Display IP. They architect and maintain systems for metrics collection and collaborate with design verification teams to optimize verification infrastructure. William holds a Bachelor of Engineering in Computer Engineering from McMaster University, where they achieved a 3.7 GPA. Prior to their position at AMD, they gained experience as a Full Stack Engineer Intern and Network Engineer Intern at Bell, as well as a Swim Instructor for the City of Toronto.