Ivan Milošević is a Senior Design Verification Engineer with over 7 years of experience in building reusable, comprehensive verification environments for chip sub-modules and subsystems. Currently at Innatera, Ivan applies expertise in SystemVerilog and UVM, having previously worked with renowned protocols such as AXI, JTAG, and MIPI. Ivan's professional journey includes positions at ELSYS Eastern Europe, NextSilicon, and AFRY, where they contributed to verifying complex chip architectures and functionalities. Ivan holds a degree from Elektrotehnički fakultet u Beogradu, completing their education in 2014.
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