Roberto Vigil Delgado is a Staff CPU Physical Design Engineer with a strong VLSI background gained over 13 years in High Speed Digital Design. Currently, they work at AheadComputing, focusing on Die2Die interconnection technologies, overseeing STA, Power, Noise, RV, LV, FEV, and ERC convergence. Previously, they were a Design Automation Engineer at Intel Corporation, where they developed software solutions for the Physical Design Team using Perl/Unix automation and TCL programming. Roberto holds a Bachelor of Engineering in Electrical and Electronics Engineering from Tecnologico de Monterrey, Campus Guadalajara.
Location
Guadalajara, Mexico
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