子緯 楊

子緯 楊 is a Senior Staff Design Engineer at Renesas Electronics, specializing in digital circuit design, RTL-to-Gate synthesis, and timing analysis since 2024. They previously served as a senior staff engineer at Alpha & Omega Semiconductor, where they contributed to Taiwan's first digital power chip. Prior experience includes managerial roles at SoNiX Technology and 立錡科技, focusing on various aspects of integrated circuit design and automation processes. 子緯 has a comprehensive background in IC design spanning low-power analysis, consumer electronics, and diverse peripheral communication protocols.