Paride Cappiello is an experienced Onboard System Architect at Alstom since April 2020, with a background as an Electronic Engineer at PROSE from October 2015 to March 2020 and at Edit Engineering from July 2008 to September 2015. Cappiello's expertise includes analysis of on-field returns, supervision of site acceptance tests, design and execution of test procedures, and management of customer technical notes. Notably, Cappiello has a focus on verification and validation of ATP/ATC systems in accordance with CENELEC processes for railway and tramway applications. Cappiello holds a Master's degree in Electronic Engineering from Università di Pisa.
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