Anusha Venkatesh

Anusha Venkatesh currently serves as the FPGA IP Design Engineering Manager at Altera, overseeing the management and development of Auto-Negotiation and Link Training of Ethernet IP since January 2024. Previously, Anusha was with Intel Corporation for over a decade, progressing from a Component Design Engineer Intern to FPGA IP Design Lead/Micro-architect, focusing on the design and micro-architecture of Ethernet FPGA IP. Early career experiences include work as an IBM Websphere Solution Developer at HCL Technologies and an intern at IBM India, participating in a remote mentoring program in Java programming. Anusha holds a Master's Degree in Computer Engineering from California State University-Sacramento and a Bachelor of Engineering in Telecommunications and Electronics Engineering from BMS Institute of Technology and Management.