Asim Patel

Asim Patel is currently the Director of Engineering at Altera, focusing on the Memory and IO Subsystem. With extensive experience in high-speed memory interface design, they previously held positions as a Principal Engineer at Marvell Semiconductor, where they contributed to next-generation AI accelerators, and as a Senior Design Engineer II at Xilinx, specializing in high-speed memory PHY architecture. Asim earned a Master's degree in Electrical Engineering with a concentration in Digital VLSI & Computer Architecture from the University of Southern California and a Bachelor’s degree in Electronics & Telecommunication from the University of Mumbai. Throughout their career, they have demonstrated expertise in both research and implementation across various leading technology companies.