Avinash Yadlapati

Avinash Yadlapati is a seasoned professional with over 15 years of experience in the semiconductor industry, currently serving as the FPGA IP Engineering Manager at Altera. They have held significant roles at AMD and Qualcomm, and have contributed as a Technical Lead and Project Manager at various companies, including Cyient and Mirafra Technologies. Avinash is involved in academia as a Visiting Professor at BV Raju Institute of Technology and a Visiting Research Fellow at Universiti Malaysia Perlis. They hold multiple advanced degrees, including a Master of Law and an MBA, and have a strong presence in professional organizations such as IEEE, where they are a Senior Member.