George Chen

George Chen is an experienced engineer specializing in FPGA design methodology and automation. Previously, they held roles as a Principal Hardware Engineer at Oracle and Senior Principal Engineer at Rapid Silicon, where they focused on EDA tool architecture, static timing analysis, and hardware-software co-design for FPGA products. They contributed significantly to Intel Corporation as the SOC Design Engineer, leading efforts in hardware/software co-design methodology and timing strategy. Currently, George is pursuing advanced degrees in Electrical Engineering from Stanford University while working as a Principal Engineer in SOC Logic Design at Altera.