Harshith Kumar Thirumala is a Digital Design Engineer currently working at Altera, focusing on FPGA IP software development. Prior to this role, Harshith served as a SoC Design Engineer at Intel Corporation and has gained extensive experience in RTL design and hardware/software co-design concepts. Harshith's professional journey includes positions as an Embedded Software Engineer at Databuoy Corporation and as a Technical Head at Team Clique, where they organized technical symposiums and workshops. Harshith holds a Master of Science in Computer Engineering from George Mason University and a Bachelor of Technology in Electronics and Communications Engineering from Jb Institute of Engineering and Technology.
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