Herr Bert New

Herr Bert New is currently the Design Engineering Manager at Altera, leading a dynamic team in the development and management of advanced FPGA IPs. They previously worked at Intel Corporation as a FPGA IP Soft IP Development Engineer, where they gained extensive experience in developing and deploying FPGA IP cores, collaborating with cross-functional teams, and providing expert technical support. Before their roles at Intel and Altera, they served as a Senior Executive at AIESEC, focusing on personal development and leadership in individuals. Herr Bert also has experience as an IPD R&D Engineering Intern at Altera and a Sales Assistant at CG Computers Sdn Bhd.