Michael Miller has over 35 years of experience in product definition, creation, and applications work within the semiconductor and system industries. They have held various engineering and leadership roles, including Chief Technology Officer at IDT and MoSys, where they pioneered innovations such as the Graph Memory Engine and a new class of SerDes attached monolithic memory. Miller possesses over 47 US patents and has contributed to numerous publications, demonstrating expertise in systems architecture, product verification, and technology innovation. Currently, they serve as a Segment Solutions Architect for Wireline at Altera.
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