Surinder S.

Surinder S. is a skilled micro-architecture engineer currently leading RTL integration of IPs for the Secure Device Manager at Altera since January 2024. With extensive experience at Intel Corporation from January 2019 to December 2023 as a Sr Staff Design Engineer, Surinder led full chip ESD, SEL, and LU reliability testing for Agilex mixed signal and silicon validation. Prior tenure at Xilinx from January 2013 to December 2019 involved managing technical engagements for SerDes, DDR-phy, and IO vendors, along with developing engineering micro-architecture specifications. Surinder's career commenced at Altera, where from January 2001 to December 2013, responsibilities included analyzing architecture specifications for SerDes blocks. Surinder holds a Master's degree in Electronics from Delhi University and has completed analog design courses through Stanford University’s SCPD program.