Thomas Bozic

Thomas Bozic is a Chief Analog Debug Engineer at Altera, bringing over 25 years of experience in SerDes design and FPGA validation. Previously, they served as a Lead Analog Mixed-Signal Design Engineer at Intel Corporation, where they specialized in developing high-speed I/O analog receiver architectures and mixed-signal simulations. Thomas also held roles as a Physical Design Engineer and Lead SerDes Behavioral Model Designer, focusing on the design and validation of analog mixed-signal circuits. They are currently pursuing both a Master of Engineering and a Bachelor of Engineering in Electrical and Electronics Engineering at the University of Colorado Boulder.