Victor Zhang is a seasoned software engineer with extensive experience in compiler flows and performance optimization for FPGAs. Currently employed at Altera since June 2022, Victor specializes in next-generation compiler flows for Intel FPGAs. Prior roles include Member of Technical Staff at Cerebras Systems and software engineering positions at Intel Corporation, where responsibilities encompassed planning and compiler flows, and at Altera, focusing on clocks and floorplanning. Victor's earlier experience includes software engineering during an academic internship and roles in research and education, with a solid educational background in Electrical and Computer Engineering and a Master of Engineering from the University of Toronto.
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