Vishwa Ranjan Kumar is a results-driven Senior Manager in Design Verification Engineering with nearly 19 years of experience in SoC, IP, and system-level verification. Previously, they held significant roles at companies including Cypress Semiconductor Corporation and Intel Corporation, leading teams of engineers to achieve 100% test coverage and successful project deliveries. Vishwa is currently spearheading a team of over 20 engineers at Altera, focusing on resource planning and verification processes for various advanced technologies. They hold a Master of Technology in Embedded Systems from the Birla Institute of Technology and Science, Pilani, and a Bachelor of Technology in Electrical and Electronics Engineering from Shanmugha Arts, Science, Technology and Research Academy.
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