Yu-Shan Wang is a technology strategist and solution architect with extensive experience in analog circuit design for wireless and wireline transceivers. They served as a Principal Engineer at Airoha Technology Corp., where they integrated Bluetooth transceiver power management units and designed various analog circuits. At Portland State University, they contributed as a Teaching Assistant and Research Assistant, focusing on modeling correlation for analog ICs. Currently, Yu-Shan serves as a Solutions Architect at Altera, following a tenure at Intel Corporation in various roles related to analog/RF circuit design and SoC engineering. They are also pursuing a PhD in Electrical and Electronics Engineering at Portland State University and a Master of Science at Columbia University.
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