Yuet Li

Yuet Li currently serves as a Senior Principal Engineer at Altera, starting in November 2023. Prior experience includes a notable tenure at Intel Corporation from January 2017 to December 2023, where Yuet occupied the role of Director of Power and Binsplit Technology, focusing on pre-silicon methodologies and yield modeling for FPGA products. Earlier positions at Intel from 2006 to 2016 involved various engineering roles, including Sr Staff Engineer, where oversight included performance estimation and power design constraints for major microprocessor projects. Yuet's career began with research at the University of Minnesota, leading to a Master of Science in Electrical and Electronics Engineering.